This invention relates generally to bridge rectifier circuits and is particularly directed to a lead frame for coupling four diode chips in a power bridge rectifier circuit.
Referring to FIG. 1, there is shown a simplified schematic diagram of a conventional bridge rectifier circuit 10. The bridge rectifier 10 includes four coupled diodes 12, 14, 16 and 18. The cathode of diode 18 and the anode of diode 12 are coupled to a first AC input lead 26, while the anode of diode 14 and the cathode of diode 16 are coupled to a second AC input lead 24. The unidirectional conducting nature of the diodes and the manner in which they are coupled in the bridge rectifier circuit causes an alternating input voltage provided to the diode combination as indicated in FIG. 1 to be converted to a DC, or direct voltage, output via lines 20 and 22.
Referring to FIG. 2, there is shown a perspective view of a conventional bridge rectifier corresponding to the electrical schematic of FIG. 1 incorporating four silicon, or semiconductor, chip diodes, where like reference numbers are used for identical elements in both figures. Thus, in FIG. 2 lead 22 is shown coupled to the anode upper surface of diode 16 and the anode upper surface of diode 18, while lead 20 is shown coupled to the cathode upper surface of diode 12 and the cathode upper surface of diode 14. Similarly, lead 24 is coupled to the cathode lower surface of diode 16 and the anode lower surface of diode 14, while lead 26 is coupled to the anode lower surface of diode 12 and the cathode lower portion of diode 18. Each of the conductive leads 20, 22, 24 and 26 is generally L-shaped and includes a first generally flat, elongated, linear section coupled to a diode terminal and a second cylindrical, elongated, linear section for coupling the bridge rectifier in the circuit.
Referring to FIG. 2 and to FIG. 3, which illustrates the details of the manner in which one of the diodes 18 is coupled in circuit in the bridge rectifier, it can be seen that one of the terminals, commonly the anode portion or surface, of each of the silicon chip diodes includes a grooved portion, or passivation moat, at the peripheral edge of the diode. Thus it can be seen that diodes 16 and 18 are respectively provided with passivation moats 16a and 18a which are closely spaced with respect to the edge of the diode and which extend around the entire anode surface of the diode. Similar passivation moat arrangements 12a and 14a are provided on the lower anode surfaces of diodes 12 and 14 in FIG. 2. Each of the passivation moats is coated with a dielectric material, preferably glass. The leads are attached to the diode chips by an electrically conductive die attaching material 36, most commonly a high temperature solder paste.
In some cases, a second dielectric material, commonly a silicone resin, is deposited around the lateral edges of the diode after the attaching process to further restrict migration of charge to the diode surface and thus improve device reliability. Usually, the assembled device is encapsulated in a third dielectric material, commonly an epoxy resin, which provides mechanical strength to the final part and also serves to improve the reliability of the part by protecting it from outside contamination.
The passivation moat 18a disposed about and within the anode surface of diode 18 serves to electronically isolate and provide a controlled contour to the diode junction, which eliminates premature voltage breakdown across the chip surface. The major function of the dielectric material 38 coating the groove is to prevent the migration of charge from outside the chip to the diode surface, which would degrade the electrical performance of the diode. The type of passivation moat illustrated in FIGS. 2 and 3 is termed a "half-moat" construction for reasons discussed below.
The conventional diode chip bridge described above which utilizes "half-moat" glass passivated diode chips is not capable of withstanding prolonged periods of exposure to high humidity environments, and in cases where such performance is required it would be advantageous to utilize "full-moat" passivated chips to provide higher reliability. The advantages of this type of construction are best related by a brief description of the usual methods of fabrication of each type, as given below.
"Half-moat" diodes are constructed by defining a gridwork of glass coated grooves in a semiconductor wafer and dicing the wafer into chips by cutting through the glassed grooves. "Full moat" diode chips, on the other hand, are obtained by patterning the semiconductor wafer with an array of closed glass passivated moats separated from each other by sufficient width to allow dicing through the semiconductor itself.
The humidity resistance of the "half-moat" devices is critically dependent upon the minimization of damage which may be done to the glass remaining on the chip either during the act of dicing or subsequent handling or electrical testing of the chip. Although certain dicing techniques have been developed which do not visibly fracture the glass passivation on the chips and which appear to yield devices which are satisfactory for some purposes, the fact remains that the reliability of such parts is variable, subject to the degree of control available in the cutting process. In addition, although thinner layers of glass in the groove are preferred because they are less subject to damage during dicing, they do not provide the bulk resistance to moisture that may be obtained with a thicker glass layer.
Since "full-moat" diode chips are separated by dicing through the semiconductor (well away from the junction) dicing damage in this case may be easily prevented. In addition, such chips are well known to be more rugged and resistant to surface damage (see "Epitaxial Diodes-Rectifiers Compatible With Today's Fast Switches," by A. Woodworth, Electronic Components and Applications, Vol. 6 No. 3, 1984, p. 186). Also, the glass thickness which may be used with the "full moat" chip is not restricted by dicing considerations.
Assembly of bridge diodes incorporating "full-moat" diode chips instead of "half-moat" types by the conventional method is impractical due to the presence of an excess unpassivated semiconductor portion around the edge of the chip which is electrically connected to the cathode and may easily come into electrical contact with the anode, thus providing an external current path which would have severely deleterious effects on device performance.
In addition, the prior art arrangement illustrated in FIGS. 2 and 3, in which "half-moat" diode chips are utilized, requires careful control of the amount of conductive attaching material 36 dispensed or otherwise provided to the chip/lead interface. Excessive quantities of this material applied to the top faces of the chips may cross over the edge of the chip and provide an external current path that would severely degrade device performance. Insufficient quantities of this material, on the other hand, may reduce the contact area or, especially in combination with imperfect part alignment, even result in no contact at all.
The present invention is intended to overcome the aforementioned limitations of the prior art by providing a lead frame arrangement for a bridge rectifier employing passivated silicon chip diodes which facilitates bridge rectifier manufacture, affords more reliable assembly of the bridge rectifier, provides for assembly of a higher reliability bridge rectifier, reduces the number of components in the bridge rectifier, and reduces the likelihood of diode leakage currents in the bridge rectifier circuit.